The present invention relates to voltage boosting converters and, more particularly to a double pumping voltage boosting circuit for providing an output voltage greater than a supplied input voltage and which is suited to be manufactured in integrated circuit form.
The evolution of integrated circuit technology has provided for ever smaller device geometry's with lower operating supply voltages. The lower supply voltage has resulted in advantages and disadvantages with the primary advantage being a significant reduction in power consumption. A significant disadvantage is the inability of some of the more complex functions to operate at the lower supply voltage. To facilitate these functions, a localized voltage boosting circuit is needed to supply an increased operating voltage. The voltage boosting circuit should be efficient in terms of power consumption, component count and die area while delivering an increased supply voltage with minimal amounts of ripple or distortion.
A basic voltage boosting circuit 10, that is well understood in the art, is illustrated in FIGS. 1, 2, and 2A. Circuit 10 uses two switches 12 and 24 for controlling the current flow and two capacitors 18 and 28 for boosting and storing an output voltage applied across a load resistor 30 which is derived from a supply voltage V.sub.DD supplied at an input 14. The circuit operation begins by first referencing the boosting capacitor 18 to the supply voltage and ground reference potential by having switch 12 closed during the first half cycle, .eta..sub.1, in response to a pair of non-overlapping clock signals C1 and C2, which are 180 degrees out of phase with respect to one another, while the output of buffer 20 is in a low voltage level state due to a boost signal applied thereto. This connects the top of capacitor 18 to V.sub.DD while the bottom is at ground reference potential. In the second half cycle, .THETA..sub.2, switch 12 opens and buffer driver output drives from a low voltage level state to a high voltage level state boosting the potential at the top of capacitor 18 to substantially twice the supply voltage V.sub.DD. Simultaneously, switch 24 closes so that the boosted charge on capacitor 18 can be distributed between itself and storing load capacitor 28. The resulting output voltage V.sub.R, depicted in FIG. 2, shows the boosted voltage on capacitor 28 decaying as current is delivered in the load R.sub.L, during the first half of the clock cycle, .THETA..sub.1. During the second half of the clock cycle, .THETA..sub.2, the output voltage first builds toward 2V.sub.DD, due to the boosted charge on capacitor 18 being redistributed across capacitors 18 and 28, and then decays as current is delivered to the load. The resulting output voltage contains a significant amount of distortion due to the discrete charge and decay times. Furthermore, it typically takes 1600 pF of capacitance for both capacitors to deliver 1.2 ma of current while boosting the voltage from 0.9 volts to 1.4 volts, at a 10 MHz clock rate.
Hence, a need exists for an improved voltage boosting circuit suitable for fabrication in integrated circuit form for boosting a supply voltage while requiring less capacitance and output voltage distortion than known prior art voltage boosting circuits.